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PMC
FEATURES
Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V * Memory Organization - Pm25LV512: 64K x 8 (512 Kbit) - PM25LV010: 128K x 8 (1 Mbit) Cost Effective Sector/Block Architecture - Uniform 4 Kbyte sectors - Uniform 32 Kbyte blocks (8 sectors per block) - Two blocks with 32 Kbytes each (512 Kbit) - Four blocks with 32 Kbytes each (1 Mbit) - 128 pages per block
Pm25LV512 / PM25LV010
512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory With 25 MHz SPI Bus Interface
Block Write Protection - The Block Protect (BP1, BP0) bits allow part or entire of the memory to be configured as read-only. Hardware Data Protection - Write Protect (WP#) pin will inhibit write operations to the status register * Page Program (up to 256 Bytes) - Typical 2 ms per page program time
Serial Peripheral Interface (SPI) Compatible - Supports SPI Modes 0 (0,0) and 3 (1,1) High Performance Read - 25 MHz clock rate (maximum)
Page Mode for Program Operations - 256 bytes per page
GENERAL DESCRIPTION
The Pm25LV512/010 are 512 Kbit/1 Mbits 3.0 Volt-only serial Flash memories. These devices are designed to use a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers as well. The device is optimized for use in many commercial applications where low-power and low-voltage operation are essential. The Pm25LV512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface consisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed.
The Pm25LV512/010 are manufactured on PMC's advanced nonvolatile CMOS technology, P-FLASHTM. The devices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.
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Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
m o .c U t4 e e h S ta a .D w w w
* Sector, Block and Chip Erase - Typical 40 ms sector/block/chip erase time Single Cycle Reprogramming for Status Register - Build-in erase before programming High Product Endurance - Guarantee 100,000 program/erase cycles per single sector (preliminary) - Minimum 20 years data retention Industrial Standard Pin-out and Package - 8-pin JEDEC SOIC - 8-contact WSON - Optional lead-free (Pb-free) packages
PMC
CONNECTION DIAGRAMS
Pm25LV512/010
CE# SO WP# GND
1 2 3 4
8 7 6 5
Vcc HOLD# SCK SI
CE# SO WP# GND
1 2 3 4
8
Vcc HOLD# SCK SI
Top View
7 6 5
8-Pin SOIC
8-Contact WSON
PIN DESCRIPTIONS
SYMB OL TYPE D ESC R IPTION C hi p Enable: C E# goes low acti vates the devi ce's i nternal ci rcui tri es for devi ce operati on. C E# goes hi gh deselects the devi ce and swi tches i nto standby mode to reduce the power consumpti on. When the devi ce i s not selected, data wi ll not be accepted vi a the seri al i nput pi n (Sl), and the seri al output pi n (SO) wi ll remai n i n a hi gh i mpedance state. Seri al D ata C lock Seri al D ata Input Seri al D ata Output Ground D evi ce Power Supply INPUT INPUT Wri te Protect: When the WP# pi n brought to low and WPEN bi t i s "1", all wri te operati ons to the status regi ster are i nhi bi ted. Hold: Pause seri al communi cati on wi th the master devi ce wi thout resetti ng the seri al sequence.
C E#
INPUT
SC K SI SO GND V cc WP# HOLD #
INPUT INPUT OUTPUT
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PMC
PRODUCT ORDERING INFORMATION
Pm25LVxxx -25 S C E
Pm25LV512/010
Environmental Attribute E = Lead-free (Pb-free) Package Blank = Standard Package Temperature Range C = Commercial (0C to +85C) Package Type S = 8-pin SOIC (8S) Q = 8-contact WSON (8Q) Operating Speed 25 MHz PMC Device Number Pm25LV512 (512 Kbit) PM25LV010 (1 Mbit)
Part Number Pm25LV512-25SCE Pm25LV512-25SC Pm25LV512-25QCE PM25LV010-25SCE PM25LV010-25SC PM25LV010-25QCE
Operating Frequency (MHz)
Package 8S
Temperature Range
25 8Q 8S 25 8Q Commercial o o (0 C to + 85 C)
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PMC
BLOCK DIAGRAM
Pm25LV512/010
SPI Chip Block Diagram
High Voltage Generator Control Logic Instruction Decoder
Serial /Parallel convert Logic
Address Latch & Counter
2KBit Page Buffer
Status Register
Y-DECODER
Memory Array
X-DECODER
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PMC
SERIAL INTERFACE DESCRIPTION
Pm25LV512/010
Pm25LV512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication term definitions are in the following section. MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave. TRANSMITTER/RECEIVER: The Pm25LV512/010 has separate pins designated for data transmission (SO) and reception (Sl). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CE# going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the Pm25LV512/010, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CE# is detected again. This will reinitialize the serial communication.
Figure 1. Bus Master and SPI Memory Devices
SDO SPI Interface with (0, 0) or (1, 1) SDI SCK SCK Bus Master SPI Memory Device CS3 CS2 CS1 CE# WP# HOLD# CE# WP# HOLD# CE# WP# HOLD# SPI Memory Device SPI Memory Device SO SI SCK SO SI SCK SO SI
Note: 1. The Write Protect (WP#) and Hold (HOLD#) si gnals should be driven, High or Low as appropriate.
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PMC
SERIAL INTERFACE DESCRIPTION (CONTINUED) SPI MODES
These devices can be driven by microcontroller with its SPI peripheral running in either of the two following modes: Mode 0 = (0, 0) Mode 3 = (1, 1) For these two modes, input data is latched in on the rising edge of Serial Clock (SCK), and output data is
Pm25LV512/010
available from the falling edge of Serial Clock (SCK). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transfering data: - Clock remains at 0 (SCK = 0) for Mode 0 (0, 0) - Clock remains at 1 (SCK = 1) for Mode 3 (1, 1)
Figure 2. SPI Modes
Mode 0 (0
0) S C K
Mode 3 (1
1) S C K
SI
SO
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PMC
DEVICE OPERATION
Pm25LV512/010
The Pm25LV512/010 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The Pm25LV512/010 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a highto-low transition. Write is defined as program and/or erase in this specification. The following commands, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE, CHIP ERASE, and WRSR are write instructions for Pm25LV512/010. Table 1. Instruction Set for the Pm25LV512/010
Instruction N ame WREN WRD I RD SR WRSR READ FAST_READ PG_ PROG SEC TOR_ERASE BLOC K_ERASE C HIP_ERASE RD ID Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 0111 1101 1000 1100 0111 1010 1011 H ex C o d e 06h 04h 05h 01h 03h 0B h 02h D 7h D 8h C 7h ABh Operation Set Wri te Enable Latch Reset Wri te Enable Latch Read Status regi ster Wri te Status Regi ster Read D ata from Memory Arrary Read D ata from Memory at Hi gher Speed Program D ata Into Memory Array Erase One Sector i n Memory Array Erase One Block i n Memory Array Erase Enti re Memory Array Read Manufacturer and Product ID
READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufacturer and product ID of the device. The instruction code is followed by three dummy bytes, each bit being latched-in on Serial Data Input (SI) during the rising edge of Serial Clock (SCK). Then the first manufacturer ID (9Dh) is shifted out on Serial Data Output (SO), followed by the device ID (7Bh = Pm25LV512; 7Ch = PM25LV010) and the second manufacturer ID (7Fh), each bit been shifted out during the falling edge of Serial Clock (SCK). Table 2. Product Identification
Product Identification Manufacturer ID Device ID: Pm25LV512 PM25LV010 7B h 7C h Data 9D h
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Pm25LV512/010
WRITE ENABLE (WREN): The device will power up in the write disable state when Vcc is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the status of the WP# pin. READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status register. The READY/ BUSY and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction. Table 3. Status Register Format
Bit 7 WPEN Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY
Table 4. Read Status Register Bit Definition
Bit Bit 0 (RDY) Definition Bit 0 = 0 indicates the device is READY . Bit 0 = 1 indicates the write cycle is in progress and the device is BUSY . Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. See Table 5. See Table 5.
Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1)
Bits 4-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) WPEN = 0 blocks the function of Write Protect pin (WP#). WPEN = 1 activates the Write Protect pin (WP#). See Table 6 for details.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection for the PM25LV010. The PM25LV010 is divided into four blocks where the top quarter (1/4), top half (1/2), or all of the memory blocks can be protected (locked out) from write. The Pm25LV512 is divided into 2 blocks where all of the memory blocks can be protected (locked out) from write. Any of the locked-out blocks will therefore be READ only. The locked-out block and the corresponding status register control bits are shown in Table 5. The three bits, BP0, BP1, and WPEN, are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, RDSR).
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Table 5. Block Write Protect Bits
Status Register Bits L evel 0 1(1/4) 2(1/2) 3(All) B P1 0 0 1 1 B P0 0 1 0 1 000000-00FFFF All Blocks (1 - 2) None None Pm25LV512 Array Addresses Locked Out Locked-out Block(s)
Pm25LV512/010
PM25LV010 Array Addresses Locked Out None 018000 - 01F F F F 010000 - 01F F F F 000000 - 01F F F F Locked-out Block(s) None Block 4 Block 3, 4 All Blocks (1 - 4)
The WRSR instruction also allows the user to enable or disable the Write Protect (WP#) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP# pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP# pin is high or the WPEN bit is "0." When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the locked-out blocks in the memory array are disabled. Write is only allowed to blocks of the memory which are not locked out. The WRSR instruction is self-timed to automatically erase and program BP0, BP1, and WPEN bits. In order to write the status register, the device must first be write enabled via the WREN instruction. Then, the instruction and data for the three bits are entered. During the internal write cycle, all instructions will be ignored except RDSR instructions. The Pm25LV512/010 will automatically return to write disable state at the completion of the WRSR cycle. Note: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP# pin is held low.
Table 6. WPEN Operation
WPEN 0 0 1 1 X X WP X X Low Low High High WEN 0 1 0 1 0 1 ProtectedBlocks Protected Protected Protected Protected Protected Protected UnprotectedBlocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable
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Pm25LV512/010
READ: Reading the Pm25LV512/010 via the SO (Serial Output) pin requires the following sequence. After the CE# line is pulled low to select a device, the READ instruction is transmitted via the Sl line followed by the byte address to be read (Refer to Table 7). Upon completion, any data on the Sl line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CE# line should be driven high after the data comes out. The READ instruction can be continued since the byte address is automatically incremented and data will continue to be shifted out. For the Pm25LV512/010, when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ instruction. FAST_READ: The device is first selected by driving CE# low. The FAST READ instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCK (Serial Clock). Then the memory contents, at that address, is shifted out on SO (Serial Output), each bit being shifted out, at a maximum frequency fFR, during the falling edge of SCK (Serial Clock). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read with a single FAST READ instruction. The FAST READ instruction is terminated by driving CE# high. PAGE PROGRAM (PG_PROG): In order to program the Pm25LV512/010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the PAGE PROGRAM instruction can be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal self-timed programming cycle, all commands will be ignored except the RDSR instruction. The PAGE PROGRAM instruction requires the following sequence. After the CE# line is pulled low to select the device, the PAGE PROGRAM instruction is transmitted via the Sl line followed by the address and the data (D7-D0) to be programmed (Refer to Table 7). Programming will start after the CE# pin is brought high. The low-to-high transition of the CE# pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a RDSR instruction. If Bit 0 = 1, the program cycle is still in progress. If Bit 0=0, the program cycle has ended. Only the RDSR instruction is enabled during the program cycle. A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. The starting byte could be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. If more than 256 bytes of data are provided, the address counter will roll over on the same page and the previous data provided will be replaced. The same byte cannot be reprogrammed without erasing the whole sector/block first. The Pm25LV512/010 will automatically return to the write disable state at the completion of the PROGRAM cycle. If the device is not write enabled (WREN) the device will ignore the Write instruction and will return to the standby state, when CE# is brought high. A new CE# falling edge is required to re-initiate the serial communication. Table 7. Address Key Note:
Address
AN Don't Care Bits
Pm25LV512
A 15 - A 0 A 23 - A 16
PM25LV010
A 16 - A 0 A 23 - A 17
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Pm25LV512/010
SECTOR_ERASE, BLOCK_ERASE: Before a byte can be reprogrammed, the sector/block which contains the byte must be erased. In order to erase the Pm25LV512/010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the SECTOR ERASE or BLOCK ERASE instruction can be executed. Table 8. Block Addresses
Block Address 000000 to 007FFF 008000 to 00FFFF 010000 to 017FFF 018000 to 01FFFF Pm25LV512 Block Block 1 Block 2 N/A N/A PM25LV010 Block Block 1 Block 2 Block 3 Block 4
The BLOCK ERASE instruction erases every byte in the selected block if the block is not locked out. Block address is automatically determined if any address within the block is selected. The BLOCK ERASE instruction is internally controlled; it will automatically be timed to completion. During this time, all commands will be ignored, except RDSR instruction. The Pm25LV512/010 will automatically return to the write disable state at the completion of the BLOCK ERASE cycle. CHIP_ERASE: As an alternative to the SECTOR and BLOCK ERASE, the CHIP ERASE instruction will erase every byte in all blocks that are not locked out. First, the device must be write enabled via the WREN instruction. Then the CHIP ERASE instruction can be executed. The CHIP ERASE instruction is internally controlled; it will automatically be timed to completion. The CHIP ERASE cycle time maximum is 100 miliseconds. During the internal erase cycle, all instructions will be ignored except RDSR. The Pm25LV512/010 will automatically return to the write disable state at the completion of the CHIP ERASE. HOLD: The HOLD# pin is used in conjunction with the CE# pin to select the Pm25LV512/010. When the device is selected and a serial sequence is underway, HOLD# pin can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD# pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD# pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the Sl pin will be ignored while the SO pin is in the high impedance state. HARDWARE WRITE PROTECT: The Pm25LV512/010 has a write lockout feature that can be activated by asserting the write protect pin (WP#). When the lockout feature is activated, locked-out sectors will be READ only. The write protect pin will allow normal read/write operations when held high. When the WP# is brought low and WPEN bit is "1", all write operations to the status register are inhibited. WP# going low while CE# is still low will interrupt a write to the status register. If the internal status register write cycle has already been initiated, WP# going low will have no effect on any write operation to the status register. The WP# pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the Pm25LV512/010 in a system with the WP# pin tied to ground and still be able to write to the status register. All WP# pin functions are enabled when the WPEN bit is set to "1".
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ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias Storage Temperature Standard Package Surface Mount Lead Soldering Temperature Lead-free Package Input Voltage with Respect to Ground on All Pins All Output Voltage with Respect to Ground VCC
(2) (2)
Pm25LV512/010
-65oC to +125oC -65oC to +125oC 240oC 3 Seconds 260oC 3 Seconds -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -0.5 V to +6.0 V
Notes: 1. Stresses under those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are VCC + 0.5 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns.
DC AND AC OPERATING RANGE
Part Number Operating Temperature Vcc Power Supply Pm25LV512/010 0o C to 85o C 2.7 V - 3.6 V
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DC CHARACTERISTICS
Applicable over recommended operating range from: TAC = 0C to +85C, VCC = +2.7 V to +3.6 V (unless otherwise noted).
Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL VIH VOL VOH Parameter Vcc Active Read Current Condition VCC = 3.6V at 25 MHz, SO = Open Min
Pm25LV512/010
Typ 10 15 0.1 0.05
Max 15 30 5 3 1 1
Units mA mA A mA A A V V V V
Vcc Program/Erase Current VCC = 3.6V at 25 MHz, SO = Open Vcc Standby Current CMOS VCC = 3.6V, CE# = VCC Vcc Standby Current TTL Input Leakage Current Output Leakage Current Input Low Voltage Input HIgh Voltage Output Low Voltage Output High Voltage 2.7V < VCC < 3.6V IOL = 2.1 mA IOH = -100 A VCC - 0.2 VCC = 3.6V, CE# = VIH to VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0 C to 85 C -0.5 0.7VCC
o o
0.8 VCC + 0.3 0.45
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AC CHARACTERISTICS
Pm25LV512/010
Applicable over recommended operating range from TA = 0C to +85C, VCC = +2.7 V to +3.6 V CL = 1TTL Gate and 30 pF (unless otherwise noted).
Symbol fFR fR tRI tFI tCKH tCKL tCEH tCS tCH tDS tDH tHS tHD tV tOH tLZ tHZ tDIS tEC tpp tw Parameter Clock Frequency for FAST_READ Clock Frequency for READ instructions Input Rise Time Input Fall Time SCK High Time SCK Low Time CE High Time CE Setup Time CE Hold Time Data In Setup Time Data in Hold Time Hold Setup Time Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Secter/Block/Chip Erase Time Page Program Time Write Status Register time 40 2 40 0 200 200 100 100 5 100 20 20 25 25 25 5 5 15 15 15 Min 0 0 Typ Max 25 20 20 20 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
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AC CHARACTERISTICS (CONTINUED)
AC WAVEFORMS(1)
Pm25LV512/010
V IH
tC E H
CE#
V IL
tC S
V IH
tC H tC K H tD S tD H VALID IN tC K L
SCK
V IL
V IH
SI
V IL
tV
V OH
tO H
tD I S
HI-Z
SO
V OL
HI-Z
Note: 1. For SPI Mode 0 (0,0)
OUTPUT TEST LOAD
INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
3.3 V
3.0 V
1.8 K OUTPUT PIN
Input 0.0 V
1.5 V
AC Measurement Level
1.3 K
30 pF
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AC CHARACTERISTICS (CONTINUED)
HOLD Timing
Pm25LV512/010
CE# tH D SCK tH S HOLD# tH Z SO tL Z tH S tH D
PIN CAPACITANCE ( f = 1 MHz, T = 25C )
Typ CIN C OUT 4 8
Max 6 12
Units pF pF
Conditions VIN = 0 V VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
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TIMING DIAGRAMS
RDID Timing
CE#
Pm25LV512/010
0
1
7
8
9
31
38
39
46
47
54
SCK
INSTRUCTION
3 Dummy Bytes
SI
1010 1011b
SO
HIGH IMPEDANCE Manufacture ID1 Device ID Manufacture ID2
WREN Timing
CE#
SCK
SI
INSTRUCTION = 0000 0110b HI-Z
SO
WRDI Timing
CE#
SCK
SI
INSTRUCTION = 0000 0100b HI-Z
SO
nnnnnnN
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RDSR Timing
CE#
Pm25LV512/010
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SI
INSTRUCTION = 0000 0101b
DATA OUT SO HIGH IMPEDANCE 7 MSB 6 5 4 3 2 1 0
WRSR Timing
CE#
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI INSTRUCTION = 0000 0001b 7 6 5
DATA IN 4 3 2 1 0
HIGH IMPEDANCE SO
READ Timing
CE#
0 SCK
1
2
3
4
5
6
7
8
9
10 11
28 29
30
31 32 33 34
35 36 37 38
3-BYTE ADDRESS SI INSTRUCTION = 0000 0011b 23 22 21
...
3
2
1
0
SO
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
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FAST READ Timing
CE#
Pm25LV512/010
0 SCK
1
2
3
4
5
6
7
8
9
10 11
28 29
30
31
3-BYTE ADDRESS SI INSTRUCTION = 0000 1011b 23 22 21
...
3
2
1
0
SO
HIGH IMPEDANCE
CE# 32 SCK 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DUMMY BYTE SI 7 6 5 4 3 2 1 0
DATA OUT 1 SO HIGH IMPEDANCE 7 6 5 4 3 2 1 0 7 6
DATA OUT 2 5 4 3 2 1 0
PAGE PROGRAM Timing
CE#
2075
2076
2077
2078 1
0 SCK
1
2
3
4
5
6
7
8
9
10 11 28 29 30 31 32 33 34
1st BYTE DATA-IN 3-BYTE ADDRESS SI INSTRUCTION = 0000 0010b 23 22 21 3 2 1 0 7 6 5 4 3 2 0
HIGH IMPEDANCE SO
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2079 256th BYTE DATA-IN
PMC
SECTOR ERASE Timing
Pm25LV512/010
CE#
0 SCK
1
2
3
4
5
6
7
8
9
10
11
28
29
30
31
3-BYTE ADDRESS SI INSTRUCTION = 1101 0111b 23 22 21
...
3
2
1
0
SO
HIGH IMPEDANCE
BLOCK ERASE Timing
CE#
0 SCK
1
2
3
4
5
6
7
8
9
10
11
28
29
30
31
3-BYTE ADDRESS SI INSTRUCTION = 1101 1000b 23 22 21
...
3
2
1
0
SO
HIGH IMPEDANCE
CHIP ERASE Timing
CE#
0
1
2
3
4
5
6
7
SCK
SI
INSTRUCTION = 1100 0111b
SO
HIGH IMPEDANCE
Programmable Microelectronics Corp.
20
Issue Date: February, 2004, Rev: 1.4
PMC
PROGRAM/ERASE PERFORMANCE
Parameter Sector Erase Time Block Erase Time Chip Erase Time Page Programming Time Unit ms ms ms ms Typ 40 40 40 2 Max 100 100 100 5
Pm25LV512/010
Remarks From writing erase command to erase completion From writing erase command to erase completion From writing erase command to erase completion From writing program command to program completion
Note: These parameters are characterized and are not 100% tested.
RELIABILITY CHARACTERISTICS (1)
Parameter Endurance Data Retention ESD - Human Body Model ESD - Machine Model Latch-Up Min 100,000 20 2,000 200 100 + ICC1
(2)
Typ
Unit Cycles Years Volts Volts mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
Note: 1. These parameters are characterized and are not 100% tested. 2. Preliminary specification only and will be formalized after cycling qualification test.
Programmable Microelectronics Corp.
21
Issue Date: February, 2004, Rev: 1.4
PMC
PACKAGE TYPE INFORMATION
Pm25LV512/010
8S 8-Pin JEDEC Small Outline Integrated Circuit (SOIC) Package (measure in millimeters)
Top View
Side View
0.51 0.33 5.00 4.80 1.27 BSC
4.00 3.80 6.20 5.80 1.75 1.35
0.25 0.10
End View
45
0.25 0.19
1.27 0.40
Programmable Microelectronics Corp.
22
Issue Date: February, 2004, Rev: 1.4
PMC
PACKAGE TYPE INFORMATION (CONTINUED)
Pm25LV512/010
8Q 8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)
Top View
Side View
5.00 BSC
6.00 BSC Pin 1 0.80 0.70
0.25 0.19
Bottom View
4.00 3.40
1.27 BSC
0.48 0.35 0.75 0.50
Programmable Microelectronics Corp.
23
Issue Date: February, 2004, Rev: 1.4
PMC
REVISION HISTORY
D ate October, 2002 D ecember, 2002 Jun, 2003 R evision N o. D escription of C hanges 1.0 1.1 1.2 New publi cati on, Preli mi nary Spec Formal Release Added WSON package opti on Added Lead-free package opti ons D ecember, 2003 1.3
Pm25LV512/010
P ag e N o . All All 1, 2, 3, 23 1, 3, 12 1, 21 22, 23 All
Upgraded guranteed program/erase cycles from 50,000 to 100,000 (preli mi nary) Updated and redrawed package di mensi on
February, 2004
1.4
Improve operati on temperature range
Programmable Microelectronics Corp.
24
Issue Date: February, 2004, Rev: 1.4

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